efabless/caravel
View on GitHub ↗ ★ 421 Verilog
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
5 mentions on Hacker News by 4 people: 0 stories, 5 comments · first 2020-11-21 · latest 2026-03-15
20082026
-
…risks, and even if I don't agree with all their decisions, I have to respect their experience. [1] https://github.com/efabless/caravel
comment by bunnie · 2026-03-15 · in Baochip-1x: What it is, why I'm doing it now and how it came about -
Those pins are not connected to the external package. See page 4 of the Caravel datasheet here: https://github.com/efabless/caravel/blob/master/doc/caravel_datasheet.pdf Only the digital I/Os are accessible from outside the package. Every…
comment by octoberfranklin · 2020-12-06 · in Google partners with SkyWater to enable open source manufacturing of ASICs -
…I/O > The user will also have access to the ESD-protected pad connections for analog signals [1] https://github.com/efabless/caravel/blob/c4c79cdf63d6a7ed7ce...
comment by rrss · 2020-12-03 · in Google partners with SkyWater to enable open source manufacturing of ASICs -
…designs, please undergrads only thanks". [1] https://europractice-ic.com/schedules-prices/ [2] https://github.com/efabless/caravel PS, It's also intensely irritating that you're forced to create a LinkedIn account and must use your…
comment by octoberfranklin · 2020-12-02 · in Google partners with SkyWater to enable open source manufacturing of ASICs -
…need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/... The openlane tool converts your verilog all the way down to final ASIC…
comment by etaioinshrdlu · 2020-11-21 · in I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM