darklife/darkriscv
View on GitHub ↗ ★ 2,640 Verilog
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
3 mentions on Hacker News by 3 people: 2 stories, 1 comment · first 2018-08-27 · latest 2025-03-16
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Opensouce RISC-V CPU core implemented in Verilog from scratch in one nightstory by delduca · 2025-03-16 · 4 comments
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Open source RISC-V implemented from scratch in one nightstory by guigg · 2018-08-27 · 109 comments