darklife/darkriscv
View on GitHub ↗ ★ 2,640 Verilog
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
3 mentions on Hacker News by 3 people: 2 stories, 1 comment · first 2018-08-27 · latest 2025-03-16
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…that call the FPGA part would be super neat. Seems small RISCV cores can be written very quickly https://github.com/darklife/darkriscv#introduction , but actually making them production hardware take a long time:…
comment by 127 · 2021-03-19 · in Designing a RISC-V CPU, Part 2: Successfully executing (some) instructions