zeroasiccorp/wildebeest
View on GitHub ↗ ★ 146 SystemVerilog
FPGA synthesis tool
4 mentions on Hacker News by 3 people: 1 story, 3 comments · first 2025-09-18 · latest 2025-09-29
20082026
-
…of explaining why. For anyone else who was wondering, it says it's under the Apache 2.0 license: https://github.com/zeroasiccorp/wildebeest?tab=Apache-2.0-1-... I didn't realize that Xilinx xc7 synthesis was officially a feature of Yosys…
comment by kragen · 2025-09-29 · in Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool -
…What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest/tree/main/archite...
comment by adapteva · 2025-09-29 · in Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool -
…b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC. https://github.com/zeroasiccorp/wildebeest
comment by adapteva · 2025-09-29 · in Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool -
▲ 2
Wildebeest RTL logic synthesis toolstory by zdw · 2025-09-18 · 0 comments