Hacker GitHub

← All repos

verilog-to-routing/vtr-verilog-to-routing

View on GitHub ↗ ★ 1,282 C++

Verilog to Routing -- Open Source CAD Flow for FPGA Research

3 mentions on Hacker News by 3 people: 0 stories, 3 comments · first 2019-11-24 · latest 2023-09-26

Mentions per year 3 mentions · busiest year 2023 (2)
20082026
AllStoriesComments NewestTopOldest
  1. …/github.com/YosysHQ/nextpnr/blob/master/docs/archapi.... ). to vpr, you must [walk the architecture]( https://github.com/verilog-to-routing/vtr-verilog-to-routing... ) to discover and cache legal placement positions. - VPR often requires…
    comment by ZirconiumX · 2023-09-26 · in Verilog to Routing
  2. …VPR paper ( https://link.springer.com/chapter/10.1007/3-540-63465-7_226 ), and the source code ( https://github.com/verilog-to-routing/vtr-verilog-to-routing... ) for more details.
    comment by stefanpie · 2023-09-26 · in Verilog to Routing
  3. Take a look at Verilog-to-Routing - an educational/research tool that is open-source. https://github.com/verilog-to-routing/vtr-verilog-to-routing
    comment by HarryBeadle · 2019-11-24 · in KiCad Joins Linux Foundation to Advance Electronic Design Automation