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ucb-bar/riscv-sodor

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educational microarchitectures for risc-v isa

7 mentions on Hacker News by 7 people: 1 story, 6 comments · first 2013-11-11 · latest 2020-06-14

Mentions per year 7 mentions · busiest year 2015 (2)
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  1. …lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/master/src/commo... In particular: - The bit patterns allocated to the simplest instructions (eg.…
    comment by haberman · 2020-06-14 · in ULX3S: Hackable FPGA that runs Linux on RISC-V
  2. …https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel) https://github.com/ucb-bar/riscv-sodor (Chisel) https://chisel.eecs.berkeley.edu/
    comment by sitkack · 2019-01-27 · in Verilog sources for Western Digital's open source RISC-V core
  3. …* BOOM (derived from Rocket) https://github.com/ucb-bar/riscv-boom * SODOR https://github.com/ucb-bar/riscv-sodor * VSCALE https://github.com/ucb-bar/vscale Anyone know of any more?
    comment by zik · 2016-03-03 · in PULPino – An open-source microcontroller system based on RISC-V
  4. …For instance the RISC-V ISA has been implemented multiple times in various languages [for instance: https://github.com/ucb-bar/riscv-sodor ]. RISC-V is quite a bit more complex than the 4004 ISA. If you want to DIY the entire chip, as in…
    comment by Gladdyu · 2015-11-16 · in SVG Mask Artwork of the Intel 4004
  5. …together a handful of different RISC-V cores that all implement the privileged/supervisor spec ( https://github.com/ucb-bar/riscv-sodor/blob/master/src/rv32_... ). Basically, detect a few cases in Decode, pass the rest of the instruction…
    comment by _chris_ · 2015-07-28 · in Show HN: A pipelined RISC-V processor written in VHDL
  6. …and different trade-offs in terms of area/performance. See for instance the 'Sodor' teaching cores https://github.com/ucb-bar/riscv-sodor https://github.com/ucb-bar/riscv-sodor/wiki which demonstrate 1-stage, 2-stage, 3-stage, 5-stage, and…
    comment by asb · 2014-12-13 · in Berkeley’s RISC-V Wants to Be Free
  7. ▲ 1
    RISC-V CPU in Chisel
    story by electronous · 2013-11-11 · 0 comments