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ucb-bar/chipyard

View on GitHub ↗ ★ 2,456 Scala

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

4 mentions on Hacker News by 4 people: 0 stories, 4 comments · first 2020-12-09 · latest 2026-01-29

Mentions per year 4 mentions · busiest year 2023 (2)
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  1. …and put in laptops and phones. [0] https://en.wikipedia.org/wiki/Chisel_(programming_language) [1] https://github.com/ucb-bar/chipyard
    comment by nish__ · 2026-01-29 · in The Sovereign Tech Fund invests in Scala
  2. …we have to write. Most of the remaining time is spent working on the physical design process. [0]: https://github.com/ucb-bar/chipyard [1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
    comment by ninjha · 2023-12-27 · in Chisel: A Modern Hardware Design Language
  3. …for humans and there's a lot of interesting work going on right now with each of them. [1] https://github.com/ucb-bar/chipyard [2] https://github.com/SpinalHDL/SpinalHDL [3] https://github.com/B-Lang-org/bsc
    comment by sweetjuly · 2023-03-05 · in Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
  4. …target ASICs. See the chipyard repository which tries to lower the learning curve a little bit : https://github.com/ucb-bar/chipyard/
    comment by ekiwi · 2020-12-09 · in IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device