travisdowns/uarch-bench
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A benchmark for low-level CPU micro-architectural features
7 mentions on Hacker News by 4 people: 4 stories, 3 comments · first 2018-01-22 · latest 2020-04-26
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Uarch-bench – a benchmark for low-level CPU micro-architectural featuresstory by simonpure · 2020-04-26 · 0 comments
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…So either your system is weird, or you weren't running enough loops, or ... I'm not sure. [1] https://github.com/travisdowns/uarch-bench
comment by BeeOnRope · 2018-11-25 · in Every 7.8μs your computer’s memory has a hiccup -
…op, so the first one that can do better than 16 bytes per cycle from any level of the cache. [1] https://github.com/travisdowns/uarch-bench/tree/master/scrip...
comment by BeeOnRope · 2018-11-20 · in How much bandwidth does the L2 have to give, anyway? -
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How much bandwidth does the L2 have to give, anyway?story by nkurz · 2018-11-20 · 12 comments
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…have fixed-latency integer dividers. [1] https://www.realworldtech.com/forum/?threadid=179004 [2] https://github.com/travisdowns/uarch-bench/wiki/Intel-Perfor...
comment by BeeOnRope · 2018-10-14 · in Uops.info: Characterizing Latency, Throughput, and Port Usage on Intel -
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Memory Disambiguation on Skylakestory by nkurz · 2018-06-25 · 1 comment
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A benchmark for low-level CPU micro-architectural featuresstory by vitaut · 2018-01-22 · 0 comments