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sylefeb/Silice

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Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

12 mentions on Hacker News by 9 people: 3 stories, 9 comments · first 2020-06-29 · latest 2026-06-03

Mentions per year 12 mentions · busiest year 2021 (6)
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  1. …ttps://www.youtube.com/watch?v=cO-Are8053g [8] : https://hackaday.com/2020/05/13/the-doom-chip/ [9] : https://github.com/sylefeb/Silice [10] : https://github.com/sylefeb/Silice/blob/master/projects/READM... [11] : doomchip article :…
    comment by sargstuff · 2026-06-03 · in Muxcard, a DIY credit card size computer
  2. …out of scope]" in the threat model. https://hackaday.com/2018/09/27/three-part-deep-dive-explain... https://github.com/sylefeb/Silice/blob/draft/projects/ice40-... > There are protections against opening it up. I'd love to see photos if…
    comment by mike_d · 2024-03-28 · in A simple, (as-of-yet unidentified) asymmetric Authenticated Key Exchange
  3. …- lookup table: https://github.com/sylefeb/gfxcat/blob/main/tunnel/tunnel.h - how it is computed: https://github.com/sylefeb/Silice/blob/master/projects/ice-v... Julia fractal, with a table to do integer multiply! (2.a.b = (a+b)^2 - a^2 -…
    comment by sylefeb · 2024-02-29 · in How video games use lookup tables
  4. In the mean time, there's the FPGA "DOOM chip" https://github.com/sylefeb/Silice/blob/master/projects/doomc... https://www.youtube.com/watch?v=2ZAIIDXoBis
    comment by corysama · 2024-01-17 · in Quake on an FPGA (MRISC32 CPU) [video]
  5. For anyone confused by the HDL, it's the author's custom language: https://github.com/sylefeb/Silice/tree/master It provides a compiler to Verilog that then can be fed to traditional design flows.
    comment by nickelpro · 2023-07-15 · in Another World ported to FPGA
  6. …the license see also discussion here https://news.ycombinator.com/item?id=27575174 and github issue https://github.com/sylefeb/Silice/issues/106
    comment by sylefeb · 2021-06-22 · in Silice: A language for hardcoding Algorithms into FPGA hardware
  7. ▲ 98
    Silice: A language for hardcoding Algorithms into FPGA hardware
    story by mleonhard · 2021-06-22 · 20 comments
  8. …of it) is not 'contaminated' by the license. There's a related issue in Silice github on this: https://github.com/sylefeb/Silice/issues/106
    comment by sylefeb · 2021-06-21 · in The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
  9. …nextpnr, edalize, openfpgaloader, verilator, icarus, ... Also, Silice comes with fun examples! https://github.com/sylefeb/Silice/tree/master/projects
    comment by sylefeb · 2021-06-21 · in The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
  10. I was more interested in the Silice project above: https://github.com/sylefeb/Silice/tree/draft
    comment by wrycoder · 2021-06-21 · in The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
  11. ▲ 75
    The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
    story by kqr2 · 2021-06-21 · 26 comments
  12. ▲ 1
    Silice, a language for hardcoding Algorithms into FPGA hardware
    story by homarp · 2020-06-29 · 0 comments