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sybreon/dcpu16

View on GitHub ↗ ★ 42 Verilog

Pipelined DCPU-16 Verilog Implementation

4 mentions on Hacker News by 2 people: 0 stories, 4 comments · first 2012-04-10 · latest 2012-04-11

Mentions per year 4 mentions · busiest year 2012 (4)
20082026
  1. …in synthesisable Verilog RTL. Synthesises to about 700+ slices at 150MHz on a Spartan6. https://github.com/sybreon/dcpu16
  2. Already done. https://github.com/sybreon/dcpu16
  3. There's already one! https://github.com/sybreon/dcpu16 The core is written entirely in synthesisable Verilog RTL. Synthesises to about 700+ Slices at around 150MHz on a Spartan6. (minus h/w division and modulo) Feel free to…
  4. If you count Verilog, there are already at least a couple[1][2]. [1]: https://github.com/sybreon/dcpu16 [2]: https://github.com/filepang/dcpu16-verilog