Hacker GitHub

← All repos

SpinalHDL/VexRiscv

View on GitHub ↗ ★ 3,301 Assembly

A FPGA friendly 32 bit RISC-V CPU implementation

17 mentions on Hacker News by 13 people: 2 stories, 15 comments · first 2017-07-19 · latest 2026-05-23

Mentions per year 17 mentions · busiest year 2017 (5)
20082026
AllStoriesComments NewestTopOldest
  1. …[0] with respect to its capabilities? I know having x86 support is a metric all by itself. [0] https://github.com/spinalhdl/vexriscv
    comment by mycall · 2026-05-23 · in z386: An Open-Source 80386 Built Around Original Microcode
  2. …It looks like the baochip-1x is using the VexRiscv CPU. The HDL is available here under MIT: https://github.com/SpinalHDL/VexRiscv
    comment by duffmancd · 2026-03-14 · in Baochip-1x: What it is, why I'm doing it now and how it came about
  3. Another opensource is https://github.com/SpinalHDL/VexRiscv
    comment by disdi · 2025-12-11 · in Qualcomm acquires RISC-V focused Ventana Micro Systems
  4. ▲ 121
    A FPGA friendly 32 bit RISC-V CPU implementation
    story by _benj · 2025-01-22 · 54 comments
  5. A CPU built around the Gentoo philosophy would look like https://github.com/SpinalHDL/VexRiscv ;). Don't want an MMU? Fine. Need a larger RAM interface? You got it. Barrel ALU for DSP? Sure. Interpreted languages work by consolidating all…
    comment by R0b0t1 · 2022-08-01 · in Faster CRC32-C on x86
  6. …Easy examples are CPUs like James Beckman's J1A, the VexRiscv design used in Bunnie's Precursor: https://github.com/SpinalHDL/VexRiscv (as little as 504 Artix-7 LUTs and 505 flip-flops), and Google's OpenTitan. But from my POV the more…
    comment by kragen · 2021-10-13 · in The 100 MHz 6502
  7. The SmallAndProductive configuration can be found here: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s... . It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all…
    comment by tverbeure · 2021-05-31 · in Open-source soft-core RISC-V SoC with gdb support
  8. …L1 I/D cache on the Xilinx FPGA - 8 MHz VexRISC-V, RV32I, no cache on the Lattice iCE40UP5K FPGA 0. https://github.com/SpinalHDL/VexRiscv 1. https://www.crowdsupply.com/sutajio-kosagi/precursor
    comment by bem94 · 2020-09-19 · in Precursor: Mobile, Open-Hardware, RISC-V System-on-Chip Development Kit
  9. …to the article - it's 100 MHz in this design. For some more performance info on Vex in general, see https://github.com/SpinalHDL/VexRiscv We've yet to make detailed analyses on the multicore version, but in general I'd say it's pretty…
    comment by thalain · 2020-05-24 · in VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA
  10. …caches and branch predictors tends to reduce the clock speed. You can find some results here: https://github.com/SpinalHDL/VexRiscv#area-usage-and-maximal... None of those numbers are for the fastest FPGAs.
    comment by tverbeure · 2020-05-21 · in VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA
  11. …Moving to an FPGA based CPU might be the next step. There are soft CPUs with cache, MMU, etc. ( https://github.com/SpinalHDL/VexRiscv for example)
    comment by tyingq · 2020-03-02 · in A Minimal TTL Processor for Architecture Exploration (1994)
  12. …bytes per transistor ? Let's look at a real CPU design it's plausible to run Fecebutt's UI on. https://github.com/SpinalHDL/VexRiscv is an LGPL-licensed RISC-V core written in SpinalHDL, an embedded DSL in Scala for hardware design. The…
    comment by kragen · 2019-12-31 · in Open Hardware on Its Own Doesn’t Solve the Trust Problem
  13. Yep and there's https://github.com/SpinalHDL/VexRiscv But admittedly, SpinalHDL is basically Chisel.
    comment by cbHXBY1D · 2017-09-26 · in BOOM v2: an open-source out-of-order RISC-V core
  14. Cached an uncached memory access are currently staticaly specified by range : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s... From 0xF000000 to 0xFFFFFFFF access will be uncached.
    comment by Dolu · 2017-07-20 · in An FPGA-friendly 32-bit RISC-V CPU implementation
  15. …plenty of open source implementations for the digital side of things. On this very github project: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s...
    comment by monocasa · 2017-07-19 · in An FPGA-friendly 32-bit RISC-V CPU implementation
  16. …slave like GPIO, UART, Timer, VGA. It's not incredible, but it's already a starting point ^^ See https://github.com/SpinalHDL/VexRiscv#briey-soc
    comment by Dolu · 2017-07-19 · in An FPGA-friendly 32-bit RISC-V CPU implementation
  17. ▲ 102
    An FPGA-friendly 32-bit RISC-V CPU implementation
    story by Dolu · 2017-07-19 · 43 comments