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SpinalHDL/VexRiscv

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A FPGA friendly 32 bit RISC-V CPU implementation

17 mentions on Hacker News by 13 people: 2 stories, 15 comments · first 2017-07-19 · latest 2026-05-23

Mentions per year 17 mentions · busiest year 2017 (5)
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  1. ▲ 121
    A FPGA friendly 32 bit RISC-V CPU implementation
    story by _benj · 2025-01-22 · 54 comments
  2. ▲ 102
    An FPGA-friendly 32-bit RISC-V CPU implementation
    story by Dolu · 2017-07-19 · 43 comments