solbjorg/oberon-riscv

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Oberon RISC-V port, based on Samuel Falvo's RISC-V compiler and Peter de Wachter's Project Norebo. Part of an academic project to evaluate Project Oberon on RISC-V.

5 mentions on Hacker News by 3 people: 1 story, 4 comments · first 2020-12-21 · latest 2026-08-09

Mentions per year 5 mentions · busiest year 2020 (2)

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…this project for the first time should be aware that the earlier Oberon-on-RISC-V project < https://github.com/solbjorg/oberon-riscv > (HN discussion: < https://news.ycombinator.com/item?id=25497002 >) exists and was already discussed on…
comment by cxr · 2026-08-09 · in Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
…we still need to find some time to build an FPGA-based SoC. Currently, it runs in emulation: https://github.com/solbjorg/oberon-riscv
comment by johndoe0815 · 2022-02-25 · in Project Oberon
…Rikke described some of the challenges porting Project Oberon to RISC-V in her project report ( https://github.com/solbjorg/oberon-riscv/blob/master/report.... ). I assume that the most time-consuming task to get Project Oberon to run on…
comment by johndoe0815 · 2021-04-04 · in Ultiboberon – Oberon on bare metal Raspberry Pi
…Some details on the port and the binary size differences can be found in the project report: https://github.com/solbjorg/oberon-riscv/blob/master/report....
comment by johndoe0815 · 2020-12-21 · in Project Oberon 2013 on RISC-V