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saagarjha/TSOEnabler

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Kernel extension that enables TSO for Apple silicon processes

12 mentions on Hacker News by 12 people: 1 story, 11 comments · first 2020-07-30 · latest 2024-11-19

Mentions per year 12 mentions · busiest year 2020 (7)
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  1. Are you sure it's userspace accessible? Based on https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabl... , it's a field in ACTLR_EL1, which is explicitly (per the ARMv8 spec, at least...) not accessible to userspace (EL0)…
    comment by Syonyk · 2024-11-19 · in Why is Apple Rosetta 2 fast? (2022)
  2. …memory ordering[1,2] to obscure flag bits[3]. [1] https://news.ycombinator.com/item?id=28731534 [2] https://github.com/saagarjha/TSOEnabler [3] https://news.ycombinator.com/item?id=33635720
    comment by mananaysiempre · 2024-01-08 · in "LibreOffice is better at reading old Word files than Word"
  3. …easier [1]. It’s not just control over the software stack that makes Rosetta so performant. [1] https://github.com/saagarjha/TSOEnabler
    comment by nknealk · 2023-10-24 · in Nvidia to Challenge Intel with Arm-Based Processors for PCs
  4. …really need Rob to explain to me how Apple's processors do TSO ;) Lemme just look up TSO and... https://github.com/saagarjha/TSOEnabler ...Oh. Fair enough, my mistake :P Is there not an instruction to switch into TSO mode, though? Wouldn't…
    comment by LordDragonfang · 2022-08-26 · in Apple M2 Pro to use new 3nm process
  5. M1 implements TSO as a special mode specifically for x86 compatibility: https://github.com/saagarjha/TSOEnabler If TSO didn’t have a performance penalty, it wouldn’t need to be a separate mode. Also, it should be obvious that stricter…
    comment by layer8 · 2022-07-04 · in Ask HN: Can competitors catch up to Apple Silicon?
  6. …is managed by the kernel so that it is on for Rosetta 2 processes and off for everything else. See https://github.com/saagarjha/TSOEnabler
    comment by abbeyj · 2020-12-01 · in ARM and Lock-Free Programming
  7. …the strength of the memory model If it weren't for the following project... I'd agree with you. https://github.com/saagarjha/TSOEnabler > A kernel extension that enables total store ordering on Apple silicon, with semantics similar to…
    comment by dragontamer · 2020-11-20 · in What do RISC and CISC mean in 2020?
  8. Exhibit A: https://www.realworldtech.com/forum/?threadid=193883&curpost... Exhibit B: https://github.com/saagarjha/TSOEnabler
    comment by MrBuddyCasino · 2020-11-18 · in World of Warcraft 9.0.2 client runs natively on Apple Silicon
  9. …performance in native code. Here's a kernel extension someone built to manipulate this feature: https://github.com/saagarjha/TSOEnabler
    comment by duskwuff · 2020-11-18 · in 16-inch MBP 2x slower than M1 MacBook Air in a real-world Rust compile
  10. …from the ARM consistency model to the TSO consistency model (Total Store Order) from x86. [1] : https://github.com/saagarjha/TSOEnabler
    comment by avianes · 2020-11-17 · in Apple Silicon M1 Emulating x86 Is Still Faster Than Every Other Mac
  11. ▲ 2
    TSOEnabler – Kernel extension that enables TSO for Apple silicon processes
    story by simonpure · 2020-07-31 · 0 comments
  12. https://github.com/saagarjha/TSOEnabler
    comment by jsheard · 2020-07-30 · in Apple Silicon implements tricky x86 behaviors in hardware for faster emulation