rsd-devel/rsd
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RSD: RISC-V Out-of-Order Superscalar Processor
3 mentions on Hacker News by 3 people: 1 story, 2 comments · first 2019-12-11 · latest 2021-11-05
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…From RSD, a core designed for FPGAs written in SystemVerilog: https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R... And then there's Alibaba's recently open-sourced XuanTie C910, which contains this Verilog… wh
comment by comex · 2021-11-05 · in The surprising subtleties of zeroing a register (2012) -
Ok, we've changed the URL to that from https://github.com/rsd-devel/rsd , which doesn't give much background.
comment by dang · 2021-01-05 · in An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf] -
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RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processorstory by matt_d · 2019-12-11 · 0 comments