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Working draft of the proposed RISC-V V vector extension

24 mentions on Hacker News by 20 people: 3 stories, 21 comments · first 2018-11-20 · latest 2024-06-30

Mentions per year 24 mentions · busiest year 2022 (8)
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  1. …and its pre-ratified vector extension[1] required special compilers until very recently. [1] https://github.com/riscv/riscv-v-spec/issues/667
    comment by fellowmartian · 2024-06-30 · in Milk-V Reveals Technical Specs of Milk-V Jupiter RISC-V Mini-ITX PC
  2. https://github.com/riscv/riscv-v-spec/commit/6f702a213f29520... The github is never the place to find ratified specs. It was used for the working draft of 1.0, and will be used for the working draft of 2.0. There have already been dozens…
    comment by brucehoult · 2024-03-17 · in Working draft of the proposed RISC-V V vector extension
  3. …Here are some resources on RVV I can recommend: RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado... RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer Tutorial:…
    comment by camel-cdr · 2024-03-04 · in Scaleway launches RISC-V servers
  4. …and aimed at the embedded market, for in GPR SIMD operations for DSP type applications. [2] [0] https://github.com/riscv/riscv-v-spec/blob/master/example/st... [1] https://camel-cdr.github.io/rvv-bench-results/canmv_k230/str... [2]…
    comment by camel-cdr · 2023-12-25 · in Cray-1 vs Raspberry Pi
  5. …[3]. [0] https://github.com/riscv/riscv-bitmanip [1] https://github.com/riscv/riscv-profiles [2] https://github.com/riscv/riscv-v-spec [3] https://github.com/riscv/riscv-crypto/blob/master/doc/vector...
    comment by camel-cdr · 2023-08-13 · in Popcount CPU instruction (2019)
  6. …example, embedded processors for digital signal processing. https://github.com/riscv/riscv-p-spec/ https://github.com/riscv/riscv-v-spec/
    comment by cbm-vic-20 · 2023-07-23 · in riscv64 is now an official Debian architecture (rebootstrap in progress)
  7. …whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811
    comment by zozbot234 · 2022-12-17 · in Fallacies about RISC-V
  8. …becoming quite large if you consider the V and P extensions. Here's the vector instructions: https://github.com/riscv/riscv-v-spec/blob/master/inst-table... The set of RISC-V features that each CPU supports is going to be so widely varied…
    comment by sparkie · 2022-11-16 · in RISC-V: The Last ISA?
  9. …thub.com/WebAssembly/flexible-vectors/blob/master/... are a better solution. They are a lot like RVV; https://github.com/riscv/riscv-v-spec , research around vector processing is why RISC-V exists in the first place! I was trying to find…
    comment by sitkack · 2022-07-25 · in Take more screenshots
  10. Also worth reading this issue: https://github.com/riscv/riscv-v-spec/issues/617 I think it's a fascinating discussion. There's been some disquiet at this design choice amongst a minority for a while from what I can tell. Who will be proven…
    comment by gchadwick · 2022-07-11 · in Concerns over mask register design in RISC-V Vector Extension v1.0
  11. …about why it was done this way, and how it makes sense. Just scroll a bit down to read it: https://github.com/riscv/riscv-v-spec/issues/811#issuecommen... I don’t know much about this, I’m a programmer, but the explanation makes sense to…
    comment by AlbertoGP · 2022-07-11 · in The Problem with RISC-V V Mask Bits
  12. https://github.com/riscv/riscv-v-spec/issues/811 linked in the article.
    comment by dogleash · 2022-07-11 · in The Problem with RISC-V V Mask Bits
  13. Github issue tracking this comment: https://github.com/riscv/riscv-v-spec/issues/811
    comment by fyrn- · 2022-07-11 · in The Problem with RISC-V V Mask Bits
  14. …RISC-V have an add-with-carry instruction as part of the vector extension? I see it listed here: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
    comment by pcwalton · 2021-12-02 · in “Risc V greatly underperforms”
  15. …of the latest specs: - Scalar crypto: https://github.com/riscv/riscv-crypto/releases - Vectors: https://github.com/riscv/riscv-v-spec/releases - Bitmanip: https://github.com/riscv/riscv-bitmanip/releases
    comment by bem94 · 2021-12-02 · in RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
  16. It looks like RVV will be going up for ratification this summer, so ( https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado... ) is pretty close to the final version.
    comment by _chris_ · 2021-05-06 · in ARM vs. RISC-V Vector Extensions
  17. …you might be tied to one of their toolchains to use it properly, rather than something upstream. 1. https://github.com/riscv/riscv-v-spec/
    comment by bem94 · 2020-11-09 · in XuanTie C906 based Allwinner RISC-V processor to power $12 Linux SBC's
  18. …following RISC-V pretty closely for the last year or so and there's quite a lot to catch up on. 1 = https://github.com/riscv/riscv-v-spec 2 = https://github.com/riscv/riscv-plic-spec
    comment by dwrodri · 2020-08-24 · in αcτµαlly pδrταblε εxεcµταblε
  19. …be migrated during execution between harts that have any difference in VLEN or ELEN parameters. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...
    comment by vlmutolo · 2020-08-07 · in Programming with RISC-V Vector Instructions
  20. …state shown in the article for the combined v1:v0 register group). [1] https://github.com/riscv/riscv-v-spec/releases/tag/0.9
    comment by nybble41 · 2020-08-07 · in Programming with RISC-V Vector Instructions
  21. …a parity bit on chip. RISC-V : spec mentions ECC, but in a phrasing that makes it clearly optional. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado... "Many processors use error correction codes in the on-chip cache, including…
    comment by mjevans · 2018-11-20 · in For a brief period, the Windows kernel tried to deal with gamma rays