Hacker GitHub

← All repos

riscv/sail-riscv

View on GitHub ↗ ★ 790 Sail

Sail RISC-V model

12 mentions on Hacker News by 7 people: 1 story, 11 comments · first 2021-12-02 · latest 2025-11-05

Mentions per year 12 mentions · busiest year 2023 (5)
20082026
AllStoriesComments NewestTopOldest
  1. Test suites: https://github.com/riscv-software-src/riscv-tests Formal model: https://github.com/riscv/sail-riscv
    comment by remexre · 2025-11-05 · in RISC-V takes first step toward international ISO/IEC standardization
  2. …I have been working on a new Rust back-end recently. [1]: https://github.com/rems-project/sail [2]: https://github.com/riscv/sail-riscv
    comment by charlycst · 2025-10-26 · in Writing a RISC-V Emulator in Rust
  3. I've used this a lot via the RISC-V Sail model: https://github.com/riscv/sail-riscv It's a really nice language - especially the lightweight dependent types. Basically it has dependent types for integers and bit-vector lengths so you can…
    comment by timhh · 2025-07-26 · in The Sail instruction-set semantics specification language
  4. ▲ 4
    Show HN: Miralis – a RISC-V virtual firmware monitor
    story by charlycst · 2025-05-10 · 0 comments
  5. …at the definition for simple instructions they can be very readable and practically pseudocode: https://github.com/riscv/sail-riscv/blob/0aae5bc7f57df4ebedd... A lot of instructions are more complex or course but that's what you get if you…
    comment by timhh · 2024-04-28 · in How to improve the RISC-V specification
  6. …formal specification of the Vector Extension has just been merged into the Golden RISC-V model: https://github.com/riscv/sail-riscv/commit/c90cf2e6eff5fa4ef... I expect that this will help stabilise compiler support and facilitate other…
    comment by Loq · 2023-11-11 · in RISC-V Vector benchmark results
  7. …instruction counters when written by software. Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256
    comment by timhh · 2023-10-23 · in Cascade: CPU fuzzing via intricate program generation
  8. …RISC-V ISA specification is not finished, you are welcome to make a PR to clarify things. [1] https://github.com/riscv/sail-riscv [2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_...
    comment by Loq · 2023-10-02 · in Arm’s Cortex A510: Two Kids in a Trench Coat
  9. …formal semantics and its type system could be unsound. https://github.com/mit-plv/riscv-coq and https://github.com/riscv/sail-riscv (don't know how complete they are) approaches actually allow to formally (mechanically) verify riscv…
    comment by nullifidian · 2023-07-29 · in F# RISC-V Instruction Set formal specification
  10. …this looks like it has been dead for 3 years so maybe it was just a precursor to the Sail model. https://github.com/riscv/sail-riscv
    comment by IshKebab · 2023-07-29 · in F# RISC-V Instruction Set formal specification
  11. …RISC-V models Spike [1] or Sail [2]? [1] https://github.com/riscv-software-src/riscv-isa-sim [2] https://github.com/riscv/sail-riscv
    comment by YorkshireSeason · 2022-11-21 · in Show HN: Libriscv – RISC-V userspace emulator library
  12. …so OS and processor need to use the same format here, which is why this is part of the ISA. [1] https://github.com/riscv/sail-riscv/tree/master/model [2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_... [3]…
    comment by YorkshireSeason · 2021-12-02 · in RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities