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RISC-V Instruction Set Manual

24 mentions on Hacker News by 17 people: 1 story, 23 comments · first 2017-06-26 · latest 2026-08-15

Mentions per year 24 mentions · busiest year 2024 (6)
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  1. https://github.com/riscv/riscv-isa-manual/pull/3269
    comment by camel-cdr · 2026-08-15 · in RISC-V: They Should Have Known Better
  2. …encode a long jump of a same range and there is a proposal for a 32-bit +32M -12M 32-bit long jump: https://github.com/riscv/riscv-isa-manual/blob/zijfal/src/un... [1] https://lists.riscv.org/g/tech-profiles/attachment/321/0/A%2... [2]…
    comment by camel-cdr · 2026-07-11 · in Book: RISC-V System-on-Chip Design
  3. …and `compare_exchange_weak` in the absolutely same way. See this issue for more information: https://github.com/riscv/riscv-isa-manual/issues/2047 - The `seed` CSR: it does not provide a good quality entropy (i.e. after you accumulated 256…
    comment by newpavlov · 2025-09-08 · in AMD claims Arm ISA doesn't offer efficiency advantage over x86
  4. e.g. this is the guarantee in RISC-V: https://github.com/riscv/riscv-isa-manual/blob/70040578316b9...
    comment by dzaima · 2025-02-14 · in Solving the ABA Problem in Rust with Tagged Pointers
  5. …the specs are getting merged into a unified isa-manual, you can get the latest version from github: https://github.com/riscv/riscv-isa-manual/releases The other project is the riscv-unified-db: https://github.com/riscv-software-src/riscv-un…
    comment by camel-cdr · 2024-11-11 · in Memory64
  6. …to address this trick[2]. [1] https://github.com/sifive/benchmark-coremark/blob/4486de1f0a... [2] https://github.com/riscv/riscv-isa-manual/issues/353
    comment by fuhsnn · 2024-10-23 · in RISC-V is currently slow compared to modern CPUs
  7. …it to behave like movsb. Still, something that could be handled by the extension instruction. [1]: https://github.com/riscv/riscv-isa-manual/releases/download/... (section 2.4.2)
    comment by magicalhippo · 2024-10-07 · in AVX Bitwise ternary logic instruction busted
  8. The handling of misaligned loads/stores in RISC-V is also can be considered a disappointing point: https://github.com/riscv/riscv-isa-manual/issues/1611 It oozes with preferring convenience of hardware developers and "flexibility" over…
    comment by newpavlov · 2024-08-27 · in Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
  9. …Zvkb, Zvbc, Zvkg, Zvkned, Zvknhb, Zvknha, Zvksed, Zvksh > massive "fill X registers from the stack" https://github.com/riscv/riscv-isa-manual/blob/176d10ada5d8c... Granted, that's optional (though, within a rounding error, all of RISC-V…
    comment by dzaima · 2024-07-19 · in Linus Torvalds says RISC-V will make the same mistakes as Arm and x86
  10. …of 2, which might require additional ports in register file only for this useless instruction). [1] https://github.com/riscv/riscv-isa-manual/releases/download/...
    comment by codedokode · 2023-06-18 · in The legend of “x86 CPUs decode instructions into RISC form internally” (2020)
  11. …for some other ISA then you'll have no trouble following straight from the RISC-V reference manual: https://github.com/riscv/riscv-isa-manual/releases/download/... Plus recently ratified extensions: https://wiki.riscv.org/display/HOME/Recen…
    comment by brucehoult · 2022-09-07 · in NASA selects SiFive and makes RISC-V the go-to ecosystem for future missions
  12. …in the spec, so as to have a possibility of encoding 64 bit literals in an 80 bit instruction. https://github.com/riscv/riscv-isa-manual/issues/280
    comment by brucehoult · 2022-04-23 · in The x86 architecture is the weirdo, part 2
  13. https://github.com/riscv/riscv-isa-manual/issues/348 suggests that the RISC-V folks are going to address this in the spec at some point.
    comment by zozbot234 · 2022-03-22 · in VRoom A high end RISC-V implementation
  14. …version for the last one (excluding the branch), but I'm not aware of it getting accepted. [1] https://github.com/riscv/riscv-isa-manual
    comment by FullyFunctional · 2022-03-20 · in Addressing Criticism of RISC-V Microprocessors
  15. …of software TLB management for an early version of the L4 microkernel on 64-bit MIPS systems. [1] https://github.com/riscv/riscv-isa-manual/releases/download/... [2] https://trustworthy.systems/publications/papers/Heiser%3AIL4...
    comment by johndoe0815 · 2022-02-26 · in Software-Refilled TLBs (1995-2007)
  16. Hypervisor seems to be covered here: https://github.com/riscv/riscv-isa-manual/blob/master/src/hy...
    comment by chem83 · 2021-12-02 · in RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
  17. …S-mode or other parts of the spec don't address per the lengthy discussion on [2]. Thanks. [1] https://github.com/riscv/riscv-isa-manual/commits/master/src... [2] https://arxiv.org/pdf/2103.14951.pdf
    comment by chem83 · 2021-06-22 · in SiFive P550 Core: High-Performance RISC-V Processor
  18. …was clarified this year. I think the author's context is moving from Bare to one of the Sv modes. https://github.com/riscv/riscv-isa-manual/commit/866326d938c...
    comment by sdbbp · 2020-12-01 · in Back That ‘S’ Up: Moving to RISC-V’s Supervisor Mode
  19. …4 bytes long. Similarly, RISC-V has variable-length instructions for extensibility. See p. 8ff of https://github.com/riscv/riscv-isa-manual/releases/download/... (section "Expanded Instruction-Length Encoding").
    comment by wolfgke · 2020-10-18 · in ARM chips have an instruction with JavaScript in the name
  20. …are no status flags, but for floating point you can check the fcsr register for exceptions [0] [0] https://github.com/riscv/riscv-isa-manual/releases/download/... EXCERPT Overflow checking for unsigned addition requires only a single…
    comment by andrekandre · 2020-09-27 · in RISC-V: What’s Missing and Who’s Competing
  21. …little too much effort to do for a drive-by comment. [0]: https://github.com/TheThirdOne/rars [1]: https://github.com/riscv/riscv-isa-manual/releases/download/... [2]: https://github.com/riscv/riscv-software-list#simulators
    comment by thethirdone · 2020-08-24 · in Implement an emulator for a fantasy CPU in JavaScript
  22. For what it's worth, the current draft of the hypervisor extensions is available here: https://github.com/riscv/riscv-isa-manual/releases/download/... and is Chapter 5 It does say this: The hypervisor extension has been designed to be…
    comment by jesse_m · 2020-07-23 · in Verified seL4 on secure RISC-V processors
  23. Yes, indeed it is about ring-0, hypervisor type stuff. https://github.com/riscv/riscv-isa-manual/blob/master/releas...
    comment by fnord123 · 2017-06-26 · in 6th RISC-V Workshop Proceedings