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riscv/riscv-bitmanip

View on GitHub ↗ ★ 221 Makefile

Working draft of the proposed RISC-V Bitmanipulation extension

17 mentions on Hacker News by 16 people: 1 story, 16 comments · first 2019-06-08 · latest 2025-02-09

Mentions per year 17 mentions · busiest year 2019 (5)
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  1. …to be nice to people reading RISC-V assembly, but I am not sure if anything will come of it: https://github.com/riscv/riscv-bitmanip/issues/185 I do not know if any x86 CPUs recognize the implicit cmov idiom offhand, but if any do, then…
    comment by ryao · 2025-02-09 · in Don't "optimize" conditional moves in shaders with mix()+step()
  2. …that the vector crypto extension will likely introduce a element wise popcount instruction [3]. [0] https://github.com/riscv/riscv-bitmanip [1] https://github.com/riscv/riscv-profiles [2] https://github.com/riscv/riscv-v-spec [3]…
    comment by camel-cdr · 2023-08-13 · in Popcount CPU instruction (2019)
  3. Here's the ratified spec[1]. And some class slides[2]. And a list of other recent extensions[3]. [1] https://github.com/riscv/riscv-bitmanip/releases/download/1.... from https://github.com/riscv/riscv-bitmanip/releases . [2]…
    comment by mncharity · 2023-01-14 · in TinyEMU – x86 and RISC-V emulator, small and simple while being complete
  4. These are the cpop and cpopw instructions. https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/i...
    comment by cbm-vic-20 · 2022-12-13 · in A neat XOR trick
  5. Yoe maybe interested in the just ratified "RISC-V Bit-Manipulation ISA-extensions" https://github.com/riscv/riscv-bitmanip/releases/download/1....
    comment by Pet_Ant · 2021-12-02 · in RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
  6. …- Vectors: https://github.com/riscv/riscv-v-spec/releases - Bitmanip: https://github.com/riscv/riscv-bitmanip/releases
    comment by bem94 · 2021-12-02 · in RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
  7. https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/_...
    comment by rwmj · 2021-09-10 · in HiFive Unmatched – A RISC-V Linux development platform
  8. I guess these are the bitmanip stuff you mention https://github.com/riscv/riscv-bitmanip They're a proposal only (and I don't think they're an official proposal), and having read them it seems the guy just shoehorned in anything he could…
    comment by throwaway_pdp09 · 2020-09-27 · in RISC-V: What’s Missing and Who’s Competing
  9. …ARMv8 bfi . It's only been added since the 0.92 draft but it seems to me very un-RISC-like. [1] https://github.com/riscv/riscv-bitmanip
    comment by CalChris · 2020-09-26 · in RISC-V: What’s Missing and Who’s Competing
  10. …With the addition of this operation there's no longer a need to use "0/-1" instead of "0/1". [1]: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip... page 36 PS: You may notice that there's also an operation (cmix: conditional…
    comment by avianes · 2020-07-24 · in Will RISC-V Revolutionize Computing?
  11. The B extension is going to add that. https://github.com/riscv/riscv-bitmanip Also conditional move which you really need for a lot of reasons but especially to avoid timing attacks in cryptography.
    comment by Symmetry · 2020-07-08 · in Ariane RISC-V CPU – An open source CPU capable of booting Linux
  12. …other hand the instruction set extensions can be bulky. For instance the bit manipulation set at https://github.com/riscv/riscv-bitmanip adds frequently used operations like conditional move and population count, but also adds things like…
    comment by tveita · 2020-03-02 · in Open Source Hardware: The Rise of RISC-V
  13. At least for binary matrix multiplication there is precedent: https://github.com/riscv/riscv-bitmanip/wiki/bitmat
    comment by legulere · 2019-06-22 · in Avoiding Instruction Cache Misses
  14. I am waiting until the Bitmanip extension lands to get excited about RISC-V: https://github.com/riscv/riscv-bitmanip Just can't live without that popcount.
    comment by ncmncm · 2019-06-19 · in Debian Riscv64 port in mid 2019
  15. …and encoding algorithms that may then run up to N times faster. The document is maintained at https://github.com/riscv/riscv-bitmanip/ .
    comment by ncmncm · 2019-06-10 · in RISC-V Bitmanip Extension [pdf]
  16. The B extension isn't tabled, it's active again: https://github.com/riscv/riscv-bitmanip
    comment by garmaine · 2019-06-08 · in Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor