olofk/serv on Hacker News

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story by kristianpaul · 2026-10-08 · 1 comment

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story by Bluestein · 2026-09-02 · 0 comments

…e.g. SERV which only takes up 198 LUTs on ice40,[1] leaving plenty of space to do other things. [1] https://github.com/olofk/serv

comment by em3rgent0rdr · 2026-09-02 · in WebFPGA (2019)

…to the SERV github in reference 38: 38. Kindgren, O. et al. SERV - The SErial RISC-V CPU. GitHub http:/github.com/olofk/serv (2020).

comment by lelandbatey · 2025-04-11 · in A 32-bit processor made with an atomically thin semiconductor

…is just a renaming of my CPU, SERV. They even pasted in block diagrams from my documentation. [0] https://github.com/olofk/serv [1] https://www.electronicsweekly.com/news/business/2d-32-bit-ri...

comment by ohazi · 2025-04-11 · in A 32-bit processor made with an atomically thin semiconductor

…CPU that can range from doing calculations just 1 bit at a time up to doing them 4 bits at a time. https://github.com/olofk/serv It's pretty incredible considering the 6502 was already considered tiny when it was released with just ~4500…

comment by hajile · 2024-09-29 · in A Bendy RISC-V Processor

…who don't know SERV is a serial RISC-V architecture - really small, fits in a Tiny Tapeout tile https://github.com/olofk/serv

comment by Taniwha · 2024-09-29 · in A Bendy RISC-V Processor

…work to do w.r.t. performance/Watt, probably more so given that the CPU seems to be bit serial ( https://github.com/olofk/serv ), which I think means an addition takes 32 cycles.

comment by Someone · 2024-09-29 · in A Bendy RISC-V Processor

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SERV – The SErial RISC-V CPU

story by peter_d_sherman · 2024-08-08 · 2 comments

…something with a few more pins), you can probably fit olof kindgren's serv implementation of risc-v https://github.com/olofk/serv into about a third of it and probably get over a mips out of it. but the total amount of block ram is 7…

comment by kragen · 2024-05-20 · in C Style: My favorite C programming practices (2014)

…that don't support it are special purpose soft cores. C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file Supports M and C extensions https://github.com/YosysHQ/picorv32 Another sized optimized…

comment by sitkack · 2024-04-30 · in RISC-V support in Android just got a big setback

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SERV – The SErial RISC-V CPU

story by RossBencina · 2023-12-10 · 0 comments

…0. https://milkv.io/duo 1. https://codeberg.org/20-100/Awesome_RISC-V/src/branch/master... 2. https://github.com/olofk/serv

comment by snvzz · 2023-10-14 · in Linux on RISC-V on Arduino Uno

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SERV: A bit-serial RISC-V core

story by adwn · 2023-06-28 · 0 comments

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SERV – open-source Tiny SErial RISC-V CPU

story by peter_d_sherman · 2023-06-14 · 1 comment

…makes even ZPU seem speedy... The ZPU uses 442 LUTs[3]. [1] https://github.com/YosysHQ/picorv32 [2] https://github.com/olofk/serv [3] https://opencores.org/projects/zpu

comment by dmitrygr · 2023-04-14 · in Zylin ZPU: 32 bit CPU with GCC toolchain

…clock to save power, so clock speed isn't everything. Olof Kindgren's bit-serial RISC-V core SeRV https://github.com/olofk/serv reputedly fits into 200 4-LUTs like those in the Lattice iCE40LP384, which would cost US$1.82–2.15 at Digi-Key…

comment by kragen · 2022-11-01 · in Qualcomm says ARM to prohibit proximity of CPU and 3rd-party modules in one chip

…a CPU of a given ISA. A basic RV32 CPU is down to 500-700 LUT. https://github.com/YosysHQ/picorv32 https://github.com/olofk/serv A minimal 8051 requires about 300 LUT. https://github.com/MicroCoreLabs/Projects/tree/master/MCL51 Not sure…

comment by jpfr · 2022-09-17 · in Apple to Move a Part of Its Embedded Cores to RISC-V

There are oh-so-many, but the one you think of might be Olof's SERV ( https://github.com/olofk/serv )

comment by FullyFunctional · 2022-07-01 · in What? More 8-Bit Microcontrollers?

…part of how it can fit into 200 4-input LUTs. Trap handling is also not part of the base ISA. https://github.com/olofk/serv#good-to-know

comment by kragen · 2022-06-21 · in RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021

…space- or power-efficient. Results might have been better with a more modern CPU design like SERV ( https://github.com/olofk/serv ).

comment by duskwuff · 2022-05-09 · in Reincarnating the 6502 Using Flexible TFT Tech for IoT

…FSMs. Today you could use a number of RISC-V implementations (the SERV for example is really tiny: https://github.com/olofk/serv ) or other soft CPU cores. But the Nios was really great when it came, esp Nios II, which removed the issue of…

comment by JoachimS · 2021-10-06 · in Nios V – Intel's RISC-V Processor

…at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: https://github.com/olofk/serv From time to time, I have been tempted to design a RISC-V implementation out of discrete 74xx components.…

comment by retrac · 2021-03-20 · in Glacial – Microcoded RISC-V core designed for low FPGA resource utilization

Maybe related, there is also SERV, a bit-serial RISC-V CPU https://github.com/olofk/serv

comment by pantalaimon · 2021-02-06 · in A one-bit processor explained: reverse-engineering the vintage MC14500B

see also https://github.com/olofk/serv for small core!

comment by homarp · 2020-12-08 · in IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device

…for the RAMs.. save even more space. BTW, there is a RISC-V bit-serial CPU (so you can use GCC): https://github.com/olofk/serv I don't know how big, but they are certainly targeting tiny FPGAs.

comment by jhallenworld · 2020-09-12 · in Show HN: Bit Serial CPU

Here is a bit serial RISC-V: https://github.com/olofk/serv

comment by jecel · 2019-08-14 · in Building a vacuum tube computer