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lowRISC/ibex

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Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

16 mentions on Hacker News by 11 people: 2 stories, 14 comments · first 2019-11-05 · latest 2026-06-14

Mentions per year 16 mentions · busiest year 2020 (4)
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  1. …https://openhwfoundation.org/ Or because its part of OpenTitan, Ibex sees a lot of development: https://github.com/lowRISC/ibex
    comment by panick21 · 2025-10-29 · in Berkeley Out-of-Order RISC-V Processor (Boom) (2020)
  2. …with the hazard 3 RISCV core https://github.com/Wren6991/Hazard3 . Of course it they'd used Ibex https://github.com/lowrisc/ibex the RISC-V core we develop and maintain at lowRISC that would have been even better but you can't have…
    comment by gchadwick · 2024-08-08 · in I got almost all of my wishes granted with RP2350
  3. …https://github.com/YosysHQ/picorv32 Another sized optimized core with C extension support https://github.com/lowrisc/ibex C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html This one should get your…
    comment by sitkack · 2024-04-30 · in RISC-V support in Android just got a big setback
  4. …CPUs (I worked on the A55, A510 and E1 at arm, focussed on memory systems and now work on Ibex: https://github.com/lowrisc/ibex amongst other things) bugs and other issues around pipelining are often to do with stall conditions, I wonder…
    comment by gchadwick · 2024-03-05 · in Filament – A Language for Fearless Hardware Design
  5. …had people consider Ibex for space applications, well verified and has a dual-core lockstep option: https://github.com/lowRISC/ibex . An ETH Zurich team have done a triple core lockstep version for cubesats:…
    comment by gchadwick · 2023-10-24 · in The risk of RISC-V: What's going on at SiFive?
  6. …embedded applications that I know has been included in multiple ASIC and FPGA designs successfully. https://github.com/lowRISC/ibex
    comment by taway32r41 · 2023-09-06 · in SiFive’s P870 Takes RISC-V Further
  7. …are high. Specially when there are very competitive verified opensource cores as well. Ibex: https://github.com/lowRISC/ibex Used by Google in the OpenTitan Project Open Hardware Group: https://www.openhwgroup.org/ Chips Alliance:…
    comment by panick21_ · 2023-03-26 · in Arm wants to charge dramatically more for chip licenses
  8. Ibex is open source and has taped out - https://github.com/lowRISC/ibex
    comment by aappleby · 2022-12-23 · in RISC-V Pushes into the Mainstream
  9. …with yosys given that it has limited system verilog support? Ibex needed to add a pass with sv2v https://github.com/lowRISC/ibex/tree/master/syn
    comment by tsmi · 2022-03-21 · in VRoom A high end RISC-V implementation
  10. The pretty minimal RV32EC core Ibex is estimated 15k gates: https://github.com/lowRISC/ibex But, the similarly minimal Arm Cortex M0 is, drumroll, 12k gates. Not saying this means Arm is better than RISC-V, such a small difference can…
    comment by jabl · 2022-03-02 · in RISC-V is succeeding
  11. …whilst not the smallest core is definitely at the small end has full bitmanip extension support: https://github.com/lowrisc/ibex Yes the extension isn't finalised yet but we're not expecting much change so we can tweak the implementation…
    comment by gchadwick · 2020-09-27 · in RISC-V: What’s Missing and Who’s Competing
  12. …high end (1.9 DMIPS/MHz!): https://github.com/ultraembedded/biriscv Google/lowRISC has this one: https://github.com/lowRISC/ibex I'm using picorv32 right now on Lattice ECP5- running code out of SPI-flash, but I added an instruction cache…
    comment by jhallenworld · 2020-08-05 · in System on Chip wrapping the SERV RISC-V soft processor
  13. I'm slightly surprised the author didn't mention the core I work on Ibex: https://github.com/lowRISC/ibex but maybe not too surprised as it's primary target isn't FPGA softcore, though it does work fine for this purpose. It's got an…
    comment by gchadwick · 2020-07-09 · in FPGA Softcore SoC Shootout
  14. …will be significant work in integrating things into a working system. I'll give a plug to Ibex ( https://github.com/lowRISC/ibex ) which is the core I work on, it doesn't have an MMU and is targetted at embedded applications. It's a 'real'…
    comment by gchadwick · 2020-05-21 · in VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA