lisper/cpus-caddr
View on GitHub ↗ ★ 166 Verilog
FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
8 mentions on Hacker News by 7 people: 1 story, 7 comments · first 2021-01-11 · latest 2026-03-04
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Ask HN: Porting MIT CADR to RISC-Vstory by lstevens14 · 2026-03-04 · 0 comments