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Minimax: a Compressed-First, Microcoded RISC-V CPU

8 mentions on Hacker News by 5 people: 1 story, 7 comments · first 2022-11-01 · latest 2025-04-16

Mentions per year 8 mentions · busiest year 2023 (4)
20082026
  1. …which is about equivalent to the 8080 and less than the Z80. And Graham Smecher's "Minimax" https://github.com/gsmecher/minimax is only two or three times the size of SeRV and over an order of magnitude faster. There's no reason to repeat…
  2. …almost never present without the full-size 4 byte instructions since we have one counter example: https://github.com/gsmecher/minimax This is an experimental rather than practical design that only directly implements the compressed…
  3. …This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
  4. …you want to grind your axe. [1] https://www.righto.com/2016/02/reverse-engineering-arm1-proc... [2] https://github.com/gsmecher/minimax
  5. …depending on the fabric, there's less (or no) unaddressed storage cells. The Minimax RISC-V CPU ( https://github.com/gsmecher/minimax; advertisement warning: my project) is what you get if you chase efficient mapping of FPGA memory…
    comment by gsmecher · 2023-08-04 · in A Single-Cycle 64-Bit RISC-V Register File
  6. …as SERV. (If Minimax was excluded from your post on the basis of insanity, I'm OK with that.) [1] https://github.com/gsmecher/minimax
    comment by gsmecher · 2023-04-14 · in Zylin ZPU: 32 bit CPU with GCC toolchain
  7. …use microcode, it is an option if your priority is not performance. Here are just two examples: https://github.com/gsmecher/minimax https://github.com/brouhaha/glacial