Hacker GitHub

← All repos

f4pga/prjtrellis

View on GitHub ↗ ★ 62 Python

Documenting the Lattice ECP5 bit-stream format.

6 mentions on Hacker News by 5 people: 0 stories, 6 comments · first 2018-11-20 · latest 2021-09-28

Mentions per year 6 mentions · busiest year 2020 (3)
20082026
AllStoriesComments NewestTopOldest
  1. …b.com/SymbiFlow/icestorm/blob/master/COPYING https://github.com/SymbiFlow/prjxray/blob/master/LICENSE https://github.com/SymbiFlow/prjtrellis/blob/master/COPYING (MIT)
    comment by 1MachineElf · 2021-09-28 · in Symbiflow: The GCC of the FPGA World
  2. …in addition to lattice tools, it is well supported by the open source trellis/yosys/nextpnr flow: https://github.com/SymbiFlow/prjtrellis
    comment by 5- · 2020-05-16 · in The Linux Kernel FPGA Subsystem
  3. …project trellis (a cool open source FPGA toolchain, but that's another story) example design: https://github.com/SymbiFlow/prjtrellis/tree/master/examples...
    comment by jhallenworld · 2020-03-02 · in Open Source Hardware: The Rise of RISC-V
  4. …to work on this board. It uses this "PICO RISC-V" (the entire CPU is in a single Verilog file): https://github.com/SymbiFlow/prjtrellis/tree/master/examples... I think it would be straightforward to build a Linux capable RISC-V system for…
    comment by jhallenworld · 2020-01-02 · in RISC-V Stumbling Blocks
  5. …Diamond, Altera/Intel Quartus, and Xilinx ISE/Vivado. [1] http://www.clifford.at/icestorm/ [2] https://github.com/SymbiFlow/prjtrellis [3] https://github.com/SymbiFlow/prjxray
    comment by mrsteveman1 · 2019-01-20 · in Remotely compromise devices by using bugs in Marvell Avastar Wi-Fi
  6. …[1] bitstream format or Xiling 7 one [2]. Everyone can help by documenting other formats too. [1] https://github.com/SymbiFlow/prjtrellis [2] https://github.com/SymbiFlow/prjxray
    comment by xvilka · 2018-11-20 · in Open-Source Bitstream Generation (2013) [pdf]