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Random ideas and interesting ideas for things we hope to eventually do.

16 mentions on Hacker News by 2 people: 2 stories, 14 comments · first 2018-10-10 · latest 2022-02-13

Mentions per year 16 mentions · busiest year 2019 (7)
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  1. …is a nice discussion[1] about the same in SymbiFlow[2]. I hope, they at least read through it. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://symbiflow.github.io/
    comment by xvilka · 2022-02-13 · in FPGA Interchange format to enable interoperable FPGA tooling
  2. …tools to agree on the common intermediate representation. Sadly, nothing came out of it yet. [1] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2021-07-05 · in Chisel/FIRRTL Hardware Compiler Framework
  3. …low-level hardware description language unification idea[1]. There are mostly active projects. [1] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2021-01-27 · in CircuitPython: Programming Hardware in Python
  4. …efforts[1] on building such a language either from scratch or based on something existing. [1] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2020-05-07 · in Clash: A modern, functional, hardware description language
  5. …with the code - see the bunch of ideas[2] for the project. [1] https://github.com/SymbiFlow [2] https://github.com/SymbiFlow/ideas/issues
    comment by xvilka · 2019-11-13 · in Developing open-source FPGA tools
  6. …[3] https://www.chisel-lang.org/ [4] https://www.chisel-lang.org/firrtl/ [5] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2019-10-17 · in FPGA Design for Software Engineers
  7. …to prevent many projects from reinventing the wheel, and be able to use each other's results. [1] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2019-06-23 · in FPGAs Have the Wrong Abstraction for Computing
  8. …https://github.com/The-OpenROAD-Project [8] Chisel3 https://github.com/freechipsproject/chisel3 [9] https://github.com/SymbiFlow/ideas/issues/19 [10] https://github.com/drom/awesome-hdl
    comment by xvilka · 2019-05-22 · in ARM memo tells staff to stop working with Huawei
  9. …[1] https://chisel.eecs.berkeley.edu/ [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2019-04-21 · in Fairylog: A Racket language aiming to be like Verilog
  10. …suggestion to create language/tooling neutral intermediate representation, based on FIRRTL[1]. [1] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2019-02-11 · in Google Edge TPU Devices
  11. …[2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/... [3] https://github.com/SymbiFlow/ideas/issues/19
    comment by xvilka · 2019-01-27 · in Verilog sources for Western Digital's open source RISC-V core
  12. …together. For now chip-design feels like programming in 1990 - quality of tooling is very bad. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3]…
    comment by xvilka · 2018-12-23 · in Chip Industry's Fundamental Shifts in 2018
  13. …many people see FIRRTL[2][3] as a viable candidate for this position, with some enhancements. [1] https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3]…
    comment by xvilka · 2018-12-01 · in Chip wars: China, America and silicon supremacy
  14. The SymbiFlow project seems to have an "ideas" repository at https://github.com/SymbiFlow/ideas/issues @mithro on twitter ( https://twitter.com/mithro ) sometimes posts requests for help like https://twitter.com/mithro/status/10182704675457…
    comment by fpgas4ever · 2018-10-10 · in SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flow for Various FPGAs