Hacker GitHub

← All repos

enjoy-digital/litedram

View on GitHub ↗ ★ 573 Python

Small footprint and configurable DRAM core

5 mentions on Hacker News by 4 people: 0 stories, 5 comments · first 2018-09-27 · latest 2022-04-29

Mentions per year 5 mentions · busiest year 2018 (2)
20082026
AllStoriesComments NewestTopOldest
  1. Related: https://github.com/enjoy-digital/litedram https://www.librecores.org/enjoy-digital/litedram https://www.webopedia.com/definitions/mch/ https://en.wikipedia.org/wiki/Northbridge_(computing)
    comment by peter_d_sherman · 2022-04-29 · in LiteDRAM – A fully open-source memory controller targeting LPDDR4/5 for FPGA
  2. …process: http://bjump.org [1] https://www.arm.com/-/media/global/products/flexible-access-... [2] https://github.com/enjoy-digital/litedram
    comment by mleonhard · 2020-05-02 · in Arm is offering early-stage startups free access to its chip designs
  3. …eyes it looks quite complex. It's written in Python using Migen[2] to generate the HDL. [1] https://github.com/enjoy-digital/litedram [2] https://github.com/m-labs/migen
    comment by rwmj · 2019-10-20 · in Compiling my own SPARC CPU inside a cheap FPGA
  4. …bits, and I don't think DDR4 does either. Here's an open source controller - you can see yourself: https://github.com/enjoy-digital/litedram
    comment by slededit · 2018-11-19 · in Intel Management Engine JTAG Proof of Concept
  5. …DDR3 controller to go with your open source SoC I recommend LiteDRAM. Its getting pretty polished. https://github.com/enjoy-digital/litedram
    comment by slededit · 2018-09-27 · in Designing a RISC-V CPU in VHDL: Arty S7 RPU SoC