combinatorylogic/soc
View on GitHub ↗ ★ 59 Verilog
An experimental System-on-Chip with a custom compiler toolchain.
5 mentions on Hacker News by 1 person: 1 story, 4 comments · first 2015-06-19 · latest 2015-12-21
20082026
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…Or a really small and slow one (smaller than J1, but needs more RAM): https://github.com/combinatorylogic/soc/tree/master/backends...
comment by sklogic · 2015-12-21 · in Open Source FPGA Toolchain Builds CPU -
…with some crazy ideas like mixing HDLs with a low level C code (see the Mandelbrot example here: https://github.com/combinatorylogic/soc/tree/master/backends... ) - this sort of things can become practical with a tighter integration…
comment by sklogic · 2015-10-09 · in The “high-level CPU” challenge (2008) -
…there is also mine kinda-C-based setup (but I also have a somewhat unfinished Oberon compiler too): https://github.com/combinatorylogic/soc
comment by sklogic · 2015-07-08 · in Project Oberon -
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An experimental System-on-Chip with a custom compiler toolchainstory by sklogic · 2015-06-19 · 0 comments
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…two in Verilog without having to implement the rest of the CPU. Plus a flexible compiler toolchain: https://github.com/combinatorylogic/soc (never mind it being multicycle, it was done this way for a reason, and dropping in a RISC design…
comment by sklogic · 2015-06-19 · in Designing a CPU in VHDL, Part 1: Rationale, Tools, Method