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chipsalliance/firrtl

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Flexible Intermediate Representation for RTL

13 mentions on Hacker News by 7 people: 1 story, 12 comments · first 2018-12-01 · latest 2025-01-27

Mentions per year 13 mentions · busiest year 2019 (6)
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  1. …FIRRTL and CIRT is the compiler for that [1], [2]. [1] The specification for the FIRRTL language: https://github.com/chipsalliance/firrtl-spec [2] Original FIRRTL compiler that's now been replaced by CIRT:…
    comment by teleforce · 2025-01-27 · in A FPGA friendly 32 bit RISC-V CPU implementation
  2. ▲ 2
    Firrtl – Flexible Intermediate Representation for RTL
    story by peter_d_sherman · 2023-07-15 · 1 comment
  3. Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl
    comment by transpute · 2022-02-13 · in FPGA Interchange format to enable interoperable FPGA tooling
  4. …ideas in this space or frustrated that these disparate teams aren't simply collaborating. [1]: https://github.com/chipsalliance/firrtl
    comment by gpanders · 2021-03-04 · in Lion: A formally verified, 5-stage pipeline RISC-V core
  5. …- besides Verilog the firrtl compiler can generate SMTLib or btor2 file for model checking: https://github.com/chipsalliance/firrtl/tree/master/src/main... - for ASIC development it is important to be able to replace all memories in your…
    comment by ekiwi · 2020-12-09 · in IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device
  6. …s://github.com/freechipsproject/chisel3/pull/892 - Refactor of Chisel and FIRRTL as Stages of Phases: https://github.com/freechipsproject/firrtl/pull/1005 (and others) - Aspect Oriented Programming: https://github.com/freechipsproject/chise…
    comment by seldridge · 2019-10-24 · in Chisel/FIRRTL Hardware Compiler Framework
  7. …[^4]: https://github.com/freechipsproject/chisel3/issues/1198 [^5]: https://github.com/freechipsproject/firrtl/pull/1204
    comment by seldridge · 2019-10-24 · in Chisel/FIRRTL Hardware Compiler Framework
  8. …project, etc. [1] https://symbiflow.githib.io [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/
    comment by xvilka · 2019-06-28 · in How AMD Gave China the ‘Keys to the Kingdom’
  9. …and fit among various alternatives. [1] https://bar.eecs.berkeley.edu/projects/firrtl.html [2] https://github.com/freechipsproject/firrtl
    comment by xvilka · 2019-06-24 · in FPGAs Have the Wrong Abstraction for Computing
  10. …businesses. [1] https://symbiflow.github.io/ [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/ [5] http://kicad-pcb.org/
    comment by xvilka · 2019-06-23 · in Open Source Could Be a Casualty of the Trade War
  11. …hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3]. [1] https://github.com/freechipsproject/FIRRTL [2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/... [3]…
    comment by xvilka · 2019-01-27 · in Verilog sources for Western Digital's open source RISC-V core
  12. …tps://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL [4] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...
    comment by xvilka · 2018-12-23 · in Chip Industry's Fundamental Shifts in 2018
  13. …tps://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL
    comment by xvilka · 2018-12-01 · in Chip wars: China, America and silicon supremacy