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chipsalliance/chisel

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Chisel: A Modern Hardware Design Language

12 mentions on Hacker News by 7 people: 2 stories, 10 comments · first 2019-02-02 · latest 2026-03-30

Mentions per year 12 mentions · busiest year 2019 (7)
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  1. …seemed a bit over the top. Though i guess it is a bit more mature and probably more enterprisey [1] https://github.com/chipsalliance/chisel
    comment by rzerowan · 2026-03-30 · in VHDL's Crown Jewel
  2. Chisel picked up Scala 3 support in 7.0.0 released last September ( https://github.com/chipsalliance/chisel/releases/tag/v7.0.0 ), right now they cross-compile between Scala 2 and 3 but from what I heard they should eventually move to…
    comment by gmartres · 2026-01-29 · in The Sovereign Tech Fund invests in Scala
  3. …with lowcost integrated FPGAs even if they are only a couple of hundred of logic cells. [1] https://github.com/chipsalliance/chisel/blob/main/README.md
    comment by rzerowan · 2025-12-23 · in FPGAs Need a New Future
  4. …Chisel but it looks amazing - software defines hardware via a Python-esque DSL to Verilog compiler. https://github.com/chipsalliance/chisel
    comment by metadat · 2025-02-06 · in T1: A RISC-V Vector processor implementation
  5. ▲ 156
    Chisel: A Modern Hardware Design Language
    story by nairboon · 2023-12-27 · 76 comments
  6. …1.2 which was a massive update. Notable additions include: - Asynchronous Reset/Reset Inference: https://github.com/freechipsproject/chisel3/pull/1011 - BoringUtils (synthesizable cross module references):…
    comment by seldridge · 2019-10-24 · in Chisel/FIRRTL Hardware Compiler Framework
  7. …https://github.com/chipsalliance/rocket-chip [^3]: https://github.com/ucb-bar/chisel-testers2 [^4]: https://github.com/freechipsproject/chisel3/issues/1198 [^5]: https://github.com/freechipsproject/firrtl/pull/1204
    comment by seldridge · 2019-10-24 · in Chisel/FIRRTL Hardware Compiler Framework
  8. …[1], Chisel3 [2]/FIRRTL[3], The Open ROAD[4] project, etc. [1] https://symbiflow.githib.io [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/
    comment by xvilka · 2019-06-28 · in How AMD Gave China the ‘Keys to the Kingdom’
  9. …KiCad[5] for simple projects can help for small businesses. [1] https://symbiflow.github.io/ [2] https://github.com/freechipsproject/chisel3 [3] https://github.com/freechipsproject/firrtl [4] https://theopenroadproject.org/ [5]…
    comment by xvilka · 2019-06-23 · in Open Source Could Be a Casualty of the Trade War
  10. …https://theopenroadproject.org [7] The OpenROAD https://github.com/The-OpenROAD-Project [8] Chisel3 https://github.com/freechipsproject/chisel3 [9] https://github.com/SymbiFlow/ideas/issues/19 [10] https://github.com/drom/awesome-hdl
    comment by xvilka · 2019-05-22 · in ARM memo tells staff to stop working with Huawei
  11. …mind. Therefore, I'm linking the pages regarding rationale for some of the recent HDLs: - Chisel: https://github.com/freechipsproject/chisel3/wiki/Frequently-... - MyHDL: http://www.myhdl.org/start/why.html - SpinalHDL:…
    comment by fizixer · 2019-02-12 · in Google Edge TPU Devices
  12. ▲ 2
    Chisel 3 – High Level Hardware Design Language (FPGA/ASIC)
    story by xvilka · 2019-02-02 · 0 comments