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aolofsson/oh

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Verilog library for ASIC and FPGA designers

4 mentions on Hacker News by 4 people: 2 stories, 2 comments · first 2016-01-09 · latest 2018-06-29

Mentions per year 4 mentions · busiest year 2016 (2)
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  1. …at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC. https://github.com/parallella/oh
    comment by ingenieroariel · 2018-06-29 · in Darpa invests $100M in a silicon compiler
  2. Definitely! Straightforward, especially if you use https://github.com/parallella/oh
    comment by adapteva · 2016-01-09 · in Why I will be using RISC-V in my next chip