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amaranth-lang/amaranth

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A modern hardware definition language and toolchain based on Python

12 mentions on Hacker News by 10 people: 2 stories, 10 comments · first 2020-03-13 · latest 2026-03-30

Mentions per year 12 mentions · busiest year 2021 (7)
20082026
  1. …to make HDL easier, and vendor neutral. Not sure why people were upset by mentioning the project... https://github.com/amaranth-lang/amaranth While VHDL makes a fun academic toy language, it has always been Verilog in the commercial…
    comment by Joel_Mckay · 2026-03-30 · in VHDL's Crown Jewel
  2. …but not sure where that went after the mergers. The Amaranth HDL python project does look fun =3 https://github.com/amaranth-lang/amaranth
    comment by Joel_Mckay · 2026-03-30 · in VHDL's Crown Jewel
  3. …gaming device, but if it's easy to double as a fun FPGA platform then that would be great. [1]: https://github.com/amaranth-lang/amaranth
    comment by magicalhippo · 2025-11-04 · in Show HN: Tamagotchi P1 for FPGAs
  4. …active development of nMigen has been rebranded a few months ago to Amaranth and can be found here: https://github.com/amaranth-lang/amaranth . In case people googled nMigen and came to the repository that hasn't been updated in two years.
    comment by snakke · 2022-03-21 · in VRoom A high end RISC-V implementation
  5. …about https://github.com/GlasgowEmbedded/glasgow recently, a bit of a niche kitchen sink that uses https://github.com/nmigen/nmigen/ to lower a domain-specific subset of Python 3 ( https://nmigen.info/nmigen/latest/lang.html ) into Verilog…
  6. …two "nmigen"s nowadays - the one originated in M-Labs and one under a project also called nmigen: https://github.com/nmigen/nmigen It's a fork, made for reasons, but more actively developed. whitequark (long time author/contributor) works…
    comment by edwinbalani · 2021-09-03 · in Awesome Lattice FPGA Boards
  7. …reduce it to an AND and NOT circuit (using the 'aigmap' command), then visualize it with [3] [1]: https://github.com/nmigen/nmigen [2]: https://yowasp.org [3]: https://github.com/nturley/netlistsvg
  8. …with nmigen generators to adapt to their parameterization. [0] besides Chisel, there is also https://github.com/nmigen/nmigen and https://github.com/SpinalHDL/SpinalHDL [1] https://github.com/cocotb/cocotb
  9. Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen There are lots of open-source (n)migen components available through the litex framework:…
    comment by ekiwi · 2021-04-17 · in Unifying the CUDA Python Ecosystem
  10. Could you please point [6] at https://github.com/nmigen/nmigen which is the new upstream after a hard fork? Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate…
    comment by ZirconiumX · 2020-03-13 · in Qnice – An Elegant 16 Bit Processor