YosysHQ/picorv32 on Hacker News

…something very tiny and completely understandable, and don't mind that it's 32 bit, then PicoRV32 ( https://github.com/YosysHQ/picorv32 ).

comment by rwmj · 2025-10-29 · in Berkeley Out-of-Order RISC-V Processor (Boom) (2020)

8 and 16 bit are dying pretty rapidly. You can make some pretty tiny 32 bit CPUs (e.g. https://github.com/YosysHQ/picorv32 is a RV32 with only a couple thousand transistors). On a budget optimized process node (e.g. 28nm), the core is…

comment by adgjlsfhk1 · 2025-09-02 · in The future of 32-bit support in the kernel

FPGA + a RISC-V core. There are loads around, the simplest is probably https://github.com/YosysHQ/picorv32 Learn how it works, try adding a new instruction or implementing an extension.

comment by rwmj · 2024-06-04 · in Ask HN: Going low-level – what to learn next?

…IP available core https://github.com/olofk/serv?tab=readme-ov-file Supports M and C extensions https://github.com/YosysHQ/picorv32 Another sized optimized core with C extension support https://github.com/lowrisc/ibex C extension in the 10…

comment by sitkack · 2024-04-30 · in RISC-V support in Android just got a big setback

…architectures, a new instruction is just a couple of lines of verilog to implement in the silicon: https://github.com/YosysHQ/picorv32/blob/master/picorv32.v#L... (this is the 'subtract' alu instruction decoder in pico riscv for example)

comment by londons_explore · 2024-01-18 · in How to Design an ISA

…(most instrs take over 32 cycles) makes even ZPU seem speedy... The ZPU uses 442 LUTs[3]. [1] https://github.com/YosysHQ/picorv32 [2] https://github.com/olofk/serv [3] https://opencores.org/projects/zpu

comment by dmitrygr · 2023-04-14 · in Zylin ZPU: 32 bit CPU with GCC toolchain

…free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32

comment by rwmj · 2022-11-27 · in Running a Unix-like OS on a home-built CPU with a home-built C compiler (2020)

…number of LUT required to implement a CPU of a given ISA. A basic RV32 CPU is down to 500-700 LUT. https://github.com/YosysHQ/picorv32 https://github.com/olofk/serv A minimal 8051 requires about 300 LUT.…

comment by jpfr · 2022-09-17 · in Apple to Move a Part of Its Embedded Cores to RISC-V

…more than enough for a RISC-V (as a matter of fact you can fo one in a much cheaper/smaller ice40: https://github.com/cliffordwolf/picorv32

comment by AndresNavarro · 2021-05-27 · in Build a RISC-V CPU from scratch

…and application processors. There's pcf (physical constraints file) for FPGAs (e.g. https://github.com/cliffordwolf/picorv32/blob/master/picosoc... ). There's CMSIS-SVD to describe register maps for peripherals, which is useful, but not…

comment by ohazi · 2020-11-08 · in Show HN: GUI for Configuring Pins on a Microcontroller

…/ peripherals on the same FPGA and talk to them from the CPU via a memory mapped interface. [1] https://github.com/cliffordwolf/picorv32 [2] https://github.com/cliffordwolf/picorv32/tree/master/picosoc

comment by ohazi · 2020-11-06 · in Western Digital SweRV RISC-V Core

…creating a RISC-V based ASIC SOC: https://www.youtube.com/watch?v=EsEcLZc0RO8 based on PicoRV: https://github.com/cliffordwolf/picorv32 . PicoRV is part of the efabless IP offerings. The chips will have a PicoRV harness on them.

comment by cottonseed · 2020-07-07 · in Google offers free fabbing for 130nm open-source chips

…Instruction spec which dictates additional things like the MMU and interrupt controller). [1] - https://github.com/cliffordwolf/picorv32/blob/master/picorv3...

comment by q3k · 2020-05-21 · in VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

…but it does mean that the RISC-V core is not the limiting factor for the rest of your FPGA design. https://github.com/cliffordwolf/picorv32 - The barrier to entry is low (as long as you already know GCC linker scripts). The problem with…

comment by jhallenworld · 2020-03-02 · in Open Source Hardware: The Rise of RISC-V

…Experimenting with non-mainstream CPUs: https://www.thanassis.space/myowncpu.html https://github.com/cliffordwolf/picorv32

comment by fest · 2019-11-13 · in Developing open-source FPGA tools

…processors of all sizes, code size has a big impact on performance in common types of program. [0]: https://github.com/cliffordwolf/picorv32

comment by microcolonel · 2019-02-14 · in RISC-V on the Verge of Broad Adoption

…UNIX legend, is using a verilog implementation by Clifford Wolf [1] in this FPGA board [2]. [1] https://github.com/cliffordwolf/picorv32 [2] https://www.tindie.com/products/Folknology/blackice-ii/

comment by yiyus · 2018-10-26 · in A Plan 9 C compiler for RISC-V [pdf]

…what I said above: hobbyists are free to design their own instruction sets, and good on them! [0] https://github.com/cliffordwolf/picorv32 [1] https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...…

comment by rwmj · 2018-10-04 · in About the ZipCPU

https://github.com/cliffordwolf/picorv32

comment by eigenloss · 2018-09-05 · in UPDuino: a $9.99 FPGA

…at about 100 MHz. At the bottom end you'd be looking at one of the boards supported by PicoRV32 ( https://github.com/cliffordwolf/picorv32 ), and some of those are as little as $100. If you want flashing lights as in the video then the…

comment by rwmj · 2018-02-07 · in LMARV-1: A RISC-V processor you can see [video]

There is PicoRV32 [1]. [1] https://github.com/cliffordwolf/picorv32

comment by rjsw · 2017-09-26 · in BOOM v2: an open-source out-of-order RISC-V core

…why people have invested tons of hours to re-write risc-v in pure verilog [1] and VHDL [2]. --- [1] https://github.com/cliffordwolf/picorv32 [2] https://github.com/sergeykhbr/riscv_vhdl

comment by pawadu · 2017-06-14 · in Program FPGAs with Go

Don't know your requirements, but take a look at picorv32. https://github.com/cliffordwolf/picorv32

comment by simcop2387 · 2016-12-20 · in Ask HN: What's the value proposition of RISC-V?

…at the high end. The smallest RISC-V implementation is PicoRV32 which is ridiculously small ( https://github.com/cliffordwolf/picorv32 - smallest is 725 LUTs in an FPGA). It couldn't have been done if the architecture had register windows.…

comment by rwmj · 2016-12-19 · in RISCVEMU: 128 bit RISC-V emulator

How is it different from PicoRV32? ( https://github.com/cliffordwolf/picorv32 )

comment by rwmj · 2016-11-18 · in ORCA – An implementation of RISC-V intended to target FPGAs

PicoRV32 ( https://github.com/cliffordwolf/picorv32 ) and ORCA ( https://github.com/VectorBlox/orca ) are two RISC-V implementations that nicely fit in ~2000 iCE40 LUTs. UCB-BAR V-Scale ( https://github.com/ucb-bar/vscale ) fits in ~4000…

comment by cliffordvienna · 2016-07-31 · in Brewing Up a myStorm FPGA board on the kitchen table

There is a Pico Risc-V that fits in ~2000 LUTs that can be built for the ice40: https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32/blob/master/scripts...

comment by edwintorok · 2016-07-31 · in Brewing Up a myStorm FPGA board on the kitchen table

…Those FPGAs of course run an MCU variant of RISC-V (as we started with talking about Arduino), e.g. https://github.com/cliffordwolf/picorv32

comment by pfalcon · 2016-05-17 · in Open source VPU side bootloader for Raspberry Pi

…* Rocket https://github.com/ucb-bar/rocket-chip * lowRISC ASIC http://www.lowrisc.org/ * PicoRV32 https://github.com/cliffordwolf/picorv32 * BOOM (derived from Rocket) https://github.com/ucb-bar/riscv-boom * SODOR…

comment by zik · 2016-03-03 · in PULPino – An open-source microcontroller system based on RISC-V

Icestorm and yosys are cool! Since then even more CPUs are working on ICE40: https://github.com/cliffordwolf/picorv32 Or a really small and slow one (smaller than J1, but needs more RAM): https://github.com/combinatorylogic/soc/tree/master/…

comment by sklogic · 2015-12-21 · in Open Source FPGA Toolchain Builds CPU

indeed. thanks for pointing this out. I have now fixed that typo. https://github.com/cliffordwolf/picorv32/commit/f8c96d6d37b6...

comment by cliffordvienna · 2015-09-23 · in PicoRV32 – A Size-Optimized RISC-V CPU