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Elphel/x393

View on GitHub ↗ ★ 40 Verilog

mirror of https://git.elphel.com/Elphel/x393

3 mentions on Hacker News by 2 people: 0 stories, 3 comments · first 2016-03-21 · latest 2016-04-01

Mentions per year 3 mentions · busiest year 2016 (3)
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  1. …system, do some calibration and save results in the same Verilog parameters format (same as here https://github.com/Elphel/x393/blob/master/includes/x393_cur... , just no header). Same program uses Verilog data to export C files, it uses…
    comment by Andrey_Filippov · 2016-04-01 · in Synchronizing Verilog, Python and C
  2. …RAM as Block RAM. I was able to modify the design (moving registers from inputs to outputs - https://github.com/Elphel/x393/blob/master/x393_sata/host/el... ) to force Vivado to infer correctly, but still have suspicion that it may not…
    comment by Andrey_Filippov · 2016-03-22 · in Free FPGA: Reimplement the primitives models
  3. …to Xilinx that if they don't take Free Software seriously they will start to lose customers. [1] https://github.com/Elphel/x393 [2] http://www.clifford.at/icestorm/ ----- edit: change "GPL licensed" to "open source", as a variety of…
    comment by femto · 2016-03-21 · in Free FPGA: Reimplement the primitives models