BrunoLevy/learn-fpga
View on GitHub ↗ ★ 3,761 C++
Learning FPGA, yosys, nextpnr, and RISC-V
6 mentions on Hacker News by 6 people: 1 story, 5 comments · first 2020-12-06 · latest 2025-12-04
20082026
-
…started with pretty much any hobby (even if it's just to get a link to another community). Edit: https://github.com/BrunoLevy/learn-fpga looks interesting.
comment by carlos_rpn · 2025-12-04 · in Ask HN: How does one get involved in FPGA development? -
I've followed this tutorial recently, and it's amazing: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/... The author includes detailed instruction for how to build a micro-controller in Verilog on an icestick, starting from a…
comment by PoignardAzur · 2023-11-07 · in FPGA Dev Boards for $150 or Less -
…for being long-winded. Also worth a look: FemtoRV32 Quark [0], which is written in Verilog. [0]: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
comment by gsmecher · 2022-11-01 · in Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU -
…RISC-V has already exceeded that. The smallest readable implementation is like 200 lines of code; https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/... I don't think Wasm suffers from the base extension issue you bring up. It…
comment by sitkack · 2022-07-25 · in Take more screenshots -
…RISC-V processor for FPGAs that I know of[0] needs 1.2K LUTs on ice40 FPGAs, so maybe barely [0]: https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV
comment by ignaloidas · 2021-11-23 · in Renesas enters FPGA market with the first ultra-low-power, low-cost family