YosysHQ/arachne-pnr
View on GitHub ↗ ★ 422 C++
Place and route tool for FPGAs
13 mentions on Hacker News by 6 people: 1 story, 12 comments · first 2015-05-28 · latest 2017-12-05
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Pick up where I left off with arachne-pnr [1] and work on open-source EDA tools. [1] https://github.com/cseed/arachne-pnr
comment by cottonseed · 2017-12-05 · in Ask HN: What would you do if your income was taken care of? -
…will help push the vendors to open up bitstreams and invest in open-source design tools. [0] https://github.com/cseed/arachne-pnr
comment by cottonseed · 2016-11-30 · in Developer Preview – EC2 Instances with Programmable Hardware -
…programming languages. I think there is a huge opportunity for tool development in this space. [0] https://github.com/cseed/arachne-pnr
comment by cottonseed · 2016-05-18 · in Why I don't spend time with Modern C++ anymore -
…iCE40s (the largest of which has 7680 LUTs): http://www.clifford.at/yosys/ (Verilog synthesis) https://github.com/cseed/arachne-pnr (Place and route) http://www.clifford.at/icestorm/ (Bitstream generator and programmer)
comment by badsock · 2016-04-07 · in RISC-V Offers Simple, Modular ISA -
…of one guy (Clifford Wolf): http://www.clifford.at/icestorm/ . It's worth noting that arachne-pnr ( https://github.com/cseed/arachne-pnr ) is written by a different person (Cotton Seed).
comment by ShinyCyril · 2016-03-13 · in How FPGAs work, and why you'll buy one (2013) -
…tools [2], [3] [1] https://github.com/cliffordwolf/icestorm [2] http://www.clifford.at/yosys/ [3] https://github.com/cseed/arachne-pnr
comment by plaes · 2015-12-01 · in Why FPGA manufacturers keep their bitstream formats secret -
…with the lines of QuickCheck and typed generators). [0] http://lcamtuf.coredump.cx/afl/ [1] https://github.com/cseed/arachne-pnr
comment by cottonseed · 2015-11-02 · in Fuzzing FFmpeg for fun and profit -
…They are especially attractive since they have the only fully open source toolchain: https://github.com/cseed/arachne-pnr Have fun!
comment by cottonseed · 2015-07-24 · in Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching -
…because there's a fully open source verilog to bitstream synthesis toolchain for the iCE40HX1K. https://github.com/cseed/arachne-pnr http://www.clifford.at/icestorm/
comment by kam · 2015-07-10 · in Low-Power $5 FPGA Module -
…. The only fully open FPGA toolchain I'm aware of targets Lattice/SiliconBLUE iCE40: https://github.com/cseed/arachne-pnr
comment by bri3d · 2015-07-01 · in Resurrecting the SuperH architecture -
…obligatory processor design, I recently created a open-source place and route tool for iCE40 FPGAs: https://github.com/cseed/arachne-pnr Together with Yosys (a Verilog synthesis tool): http://www.clifford.at/yosys/ and the IceStorm…
comment by cottonseed · 2015-06-19 · in Designing a CPU in VHDL, Part 1: Rationale, Tools, Method -
…IceStorm project [1]. We're using Yosys [2] for Verilog synthesis, also written by Clifford. [0] https://github.com/cseed/arachne-pnr [1] http://www.clifford.at/icestorm/ [2] http://www.clifford.at/yosys/
comment by cottonseed · 2015-06-01 · in Intel Buys Altera for $16.7B -
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Arachne-pnr: an open-source place and route tool for Lattice iCE40 FPGAsstory by cottonseed · 2015-05-28 · 0 comments