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eggie5/SDSU-COMPE475-SPRING13

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Microprocessors (Verilog)

4 mentions on Hacker News by 1 person: 0 stories, 4 comments · first 2015-06-19 · latest 2017-05-01

Mentions per year 4 mentions · busiest year 2016 (2)
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  1. …From my experience verilog was much nicer to use. I designed a complete MIPS pipelined CPU: https://github.com/eggie5/SDSU-COMPE475-SPRING13 However, speaking to many FPGA professionals I know, VHDL has a much more traction in industry and…
    comment by eggie5 · 2017-05-01 · in VHDL or Verilog?
  2. …during undergrad. It was probably the hardest and most rewarding task I've completed in my life! https://github.com/eggie5/SDSU-COMPE475-SPRING13
    comment by eggie5 · 2016-11-03 · in Why hardware development is hard, part 1: Verilog is weird (2013)
  3. …my compe w/o using windows at all. Check out the processor build all using the Icarus toolchain: https://github.com/eggie5/SDSU-COMPE475-SPRING13/tree/master...
    comment by eggie5 · 2016-04-06 · in Icarus Verilog Simulator
  4. I't s a viable concept. In school we built a functional pipelined-MIPS processor in verilog: https://github.com/eggie5/SDSU-COMPE475-SPRING13
    comment by eggie5 · 2015-06-19 · in Designing a CPU in VHDL, Part 1: Rationale, Tools, Method